Why does the Low Latency Ethernet 10G MAC IP with IEEE 1588v2 feature perform checksum correction when checksum correction control signal is not asserted for the packet? - Why does the Low Latency Ethernet 10G MAC IP with IEEE 1588v2 feature perform checksum correction when checksum correction control signal is not asserted for the packet? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, the Low Latency Ethernet 10G MAC IP with IEEE 1588v2 feature may perform checksum correct insertion to the packet when a user does not assert the checksum correct control signal if the previous packet has checksum correct insertion due to the IP's behavior. Resolution To work around this problem, force the IP input signal " tx_etstamp_ins_ctrl_offset_checksum_correction " to 16h'0000 in the RTL when checksum correction is not requested for the particular packet. Custom Fields values: ['novalue'] Troubleshooting 15015978378 False ['IP Low Latency 10-Gbps Ethernet MAC and PHY Function IP-10GEUMAC'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.2 ['Agilex™ FPGA Portfolio', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']