Why is the Intel® Stratix® 10 E-tile Hard IP for Ethernet (10G/25G) TX Timestamp error > 1 second? - Why is the Intel® Stratix® 10 E-tile Hard IP for Ethernet (10G/25G) TX Timestamp error > 1 second? Description Due to a problem in Intel® Quartus® Prime Pro version 18.0 and earlier, the Intel® Stratix® 10 E-tile Hard IP for Ethernet (10G/25G) will occasionally issue a TX timestamp that is 1 second larger than expected. This causes an inaccurate error of 1 second in the TX timestamp. Resolution A possible work around to this problem would be to compare the TX timestamp against the time-of-day(ToD), and then subtract 1 second from it if the timestamp is 1 second larger than the ToD. This problem is scheduled to be fixed in the next release of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 564199; True ['25G Ethernet IP', 'Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0.1 18.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']