Stratix® 10 SX SoC FPGA - View Stratix 10 SX SoC FPGAs and find product specifications, features, applications and more. Product Pages Industrial Medical Transportation Overview Stratix 10 SoC FPGA combines a quad-core Arm* Cortex*-A53 MPCore® hard processor system with the groundbreaking Hyperflex™ FPGA Architecture to deliver the performance, power efficiency, density, and integration required for embedded applications. Stratix 10 SX FPGA Product Table Benefits With an embedded hard processor system (HPS) based on a quad-core Arm® Cortex®-A53 MPCore® processor, Stratix 10 SoC FPGAs deliver power-efficient, application-grade performance and enable designers to implement hardware-assisted virtualization directly in the FPGA fabric. Enabling Designers to Do More with HPS While Balancing Power Efficiency Stratix 10 SoC FPGA empowers the USR in the ARM* ecosystem. ARM's next-generation 64-bit architecture (ARMv8) enables hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The ARM* Cortex-A53* processor supports 32-bit execution mode and board support packages for popular operating systems, including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more. Achieve High Levels of System Integration Optimized for multi-million logic elements (LE), the Virtual Platform streamlines design iterations, fostering early software development. C-based design with FPGA SDK for OpenCL™ offers an easy-to-implement environment on SoC FPGA. The SoC FPGA Embedded Development Suite (EDS) enables debugging, profiling, and whole-chip visualization with the ARM* Development Studio 5* (DS-5*) FPGA Edition Toolkit. Achieve High Designer Productivity with Optimized FPGA and SoC FPGA Software Key Features At the heart of the HPS is a highly efficient quad-core ARM* Cortex*-A53 processor cluster, and this processor is optimized for ultra-high performance per watt, which reduces power consumption. The HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals. Hard Processor System (HPS) With Stratix 10 devices, DSP designs can achieve up to 8.6 Tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations. Digital Signal Processing (DSP) SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks. Secure Device Manager (SDM) Applications Industrial Medical Automotive Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Stratix 10 SX SoC Development Kit Integrated ARM processing with FPGA fabric for embedded systems. IP Interlaken IP This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market. Nios V Processors By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. DDR4 External Memory Interface IP Supports high-speed memory access for balanced workloads. Software Quartus® Prime Pro Edition Design Software Documentation Documents Documentation Stratix 10 SX SoC FPGA Product Table Stratix 10 FPGAs and SoCs Quick Links Stratix 10 SX FPGA Device Overview Stratix 10 FPGA Datasheet Support Resources Stratix® 10 SX FPGA