How long does it take for the Intel® PHYLite IP output delay to take effect when performing dynamic reconfiguration? - How long does it take for the Intel® PHYLite IP output delay to take effect when performing dynamic reconfiguration? Description The time for the Intel® PHYLite IP output delay to take effect after writing a new value to the register via the Avalon bus, is dependent on the user's configuration. It will take approximately 50 VCO clock cycles, and Intel recommends that you perform an RTL simulation to obtain accurate timing which will correlate with the hardware operation. The output signal will not glitch. Custom Fields values: ['novalue'] Troubleshooting FB: 604165; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 16.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']