Why do I get unexpected output frequencies when issuing a mgmt_reset pulse before the first write operation during a dynamic reconfiguration of an Agilex™ 7 FPGA and SoC FPGA F/I-Series IOPLL? - Why do I get unexpected output frequencies when issuing a mgmt_reset pulse before the first write operation during a dynamic reconfiguration of an Agilex™ 7 FPGA and SoC FPGA F/I-Series IOPLL? Description When performing an IOPLL dynamic reconfiguration of an Agilex™ 7 FPGA and SoC FPGA F/I-Series, you may get unexpected output frequencies if you do a write/read operation less than 4 clock cycles after a mgmt_reset pulse. This is because the internal circuitry of the IOPLL is in an initialization state, and it must wait at least 4 clock cycles for it to exit such a state. Resolution After issuing a pulse to mgmt_reset , please wait at least 4 mgmt_clk clock cycles to start the dynamic reconfiguration process. Custom Fields values: ['novalue'] Troubleshooting 14022915254 False ['IOPLL Reconfig IP'] ['FPGA Dev Tools Quartus® Prime Software'] No plan to fix No plan to fix ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']