How do I make modelsim fwrite/dump an 8 bit array literally in binary. - How do I make modelsim fwrite/dump an 8 bit array literally in binary. I'm having trouble finding the right way to dump a memory array from my System Verilog testbench into a file. This is as close as I can get, but, it has 2 problems. Anytime I try to write character 8'h00, it gets replaced with character 8'h20. Anytime I try to write character 8'h0A, 2 characters come out, first 8'h0D, then 8'h0A. Code: integer fout_pointer; fout_pointer= $fopen("test_file.bin","w"); for (int i=0;i<256;i++) $fwrite(fout_pointer,"%s",8'(i)) ; $fclose(fout_pointer); This code is supposed to generate a file where if I analyze it with a hex editor, it should go from 8'h00 the 8'hFF. But, the 8'h00 position has an 8'h20 and the 8'h0A position has a 8'h0D, then the 8'h0A comes next. Or, if I made an array: logic [7:0] array_table [0:255] = '{8'h00, 8'h01, 8'h03, ..... }; Is there a way to binary dump/write that array into a file. And I do not mean an ascii file with binary or hex values in it. Replies: Re: How do I make modelsim fwrite/dump an 8 bit array literally in binary. Hello SyafieqS, thank you for your reply, but, your link does not cover any binary writing of data. It is ok as I fround out how and finally got my testbench SystemVerilog .bmp picture saver working. Source example located here: https://www.eevblog.com/forum/fpga/systemverilog-example-testbench-which-saves-a-bmp-picture-and-executes-a-script/msg3448860/#msg3448860 Instruction are located in the first post in that thread. The relevant code is in the source file 'ellipse_generator_tb.sv' line 203, opening the file for write as a 'wb' for write binary. And when $fwrite data, the two possible in quotes methods are "%c" for a single character, or "%u" for writing a 32bit word located on lines 215, 218 & 225. Replies: Re: How do I make modelsim fwrite/dump an 8 bit array literally in binary. Hi Brian, I found refence related to read and write to file using SV and few examples that might be helpful. Please refer to link below for details https://www.chipverify.com/systemverilog/systemverilog-file-io#:~:text=A%20file%20can%20be%20opened,the%20%24fclose()%20system%20task . Thanks, Regards