Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface? - Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface? Description When comparing the DQ waveforms, you may notice that the measured steady-state read waveform amplitude exceeds the expected value simulated by the IBIS model. This is due to an adjustment of the Rt termination value by the Quartus® II software where the equivalent resistance is higher than expected. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']