Why does the Synopsys VCS* simulator show packet loss on the RX Datapath when simulating the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example with IEEE 1588v2 enabled? - Why does the Synopsys VCS* simulator show packet loss on the RX Datapath when simulating the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example with IEEE 1588v2 enabled? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example for the variant 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet with IEEE 1588v2 enabled, the Synopsys VCS* simulator shows packet loss on the RX datapath due to internal path failures, this is due to the RX datapath FIFO overflow. Resolution There is no workaround to this problem in 23.4. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16023653077 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']