Does the output hold time (tCLQX) of the quad-serial configuration (EPCQ) device meet the data hold time after the falling edge on DCLK (tDH) requirement for active serial (AS) configuration in Arria® V, Stratix® V, and Cyclone® V device? - Does the output hold time (tCLQX) of the quad-serial configuration (EPCQ) device meet the data hold time after the falling edge on DCLK (tDH) requirement for active serial (AS) configuration in Arria® V, Stratix® V, and Cyclone® V device? Description Does the output hold time (tCLQX) of the quad-serial configuration (EPCQ) device meet the data hold time after the falling edge on DCLK (tDH) requirement for active serial (AS) configuration in Arria® V, Stratix® V, and Cyclone® V device? Resolution FPGA Assessment Results Arria® V GX/GT/SX/ST Yes. The EPCQ devices datasheet doesn't show the tCLQX specifications. But the Arria V GX/GT/SX/ST characterization data shows the minimum tCLQX of EPCQ device is the same as or larger than the minimum tDH requirement for AS configuration shown in the Arria® V device datasheet . Arria® V GZ device Please contact your local Field Applications Engineer (FAE) or submit a Service Request at the My Intel support page. Stratix® V GT/GX/GS/E Please contact your local FAE or submit a Service Request at the My Intel support page. Cyclone® V device Refer to the following knowledge article: Does the output hold time (tCLQX) of the quad-serial configuration (EPCQ) device meet the data hold time after the falling edge on DCLK (tDH) requirement for active serial (AS) configuration in Cyclone® V device? Custom Fields values: ['novalue'] Troubleshooting 1507081222 False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['Configuration Device EPCQ'] ['novalue']