Which clock are the tx_ready and rx_ready status signals synchronous to in the Altera Transceiver PHY IP core? - Which clock are the tx_ready and rx_ready status signals synchronous to in the Altera Transceiver PHY IP core? Description The tx_ready and rx_ready status signals are synchronous to the phy_mgmt_clk as they are generated from the embedded reset controller which runs off the phy_mgmt_clk. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV GT FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25