Why does the address range of my Qsys PIO, Interval timer and Jtag Uart change when I add a new Avalon-MM master? - Why does the address range of my Qsys PIO, Interval timer and Jtag Uart change when I add a new Avalon-MM master? Description An issue has been identified where the address range of some Altera® slave peripherals is dependant on the data-width of the largest Avalon®-MM master in the project. The following IP's may be effected: DMA Controller Remote Update Controller Alpha Blending Mixer Control Synchronizer Switch Clocked Audio Input Clocked Audio Output SPI (3 wire serial) UART JTAG Uart Mutex Performance Counter Unit Character LCD Interval Timer PIO (Parallel I/O) USB Data Streamer Controller Resolution This issue may be fixed in a future version of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']