Why am I seeing VHDL simulation failures with Xcelium*, Riviera*, and QuestaSim* simulators for the F-tile Dynamic Reconfiguration Suite IP designs? - Why am I seeing VHDL simulation failures with Xcelium*, Riviera*, and QuestaSim* simulators for the F-tile Dynamic Reconfiguration Suite IP designs? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3.1, you may see VHDL simulation failures with Xcelium*, Riviera*, and QuestaSim* simulators with “ port i_tx_pfc ” error for F-tile Dynamic Reconfiguration Suite IP designs with the following configurations: 1.) Ethernet 400G RS-FEC configurations Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1. Custom Fields values: ['novalue'] Errata 14024372189, 31020086371 False ['F-Tile Dynamic Reconfiguration Suite IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']