Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs - Same Course in Simplified Chinese: 使用Altera FPGA中的高性能存储器接口 117 Minutes Memory interface design for FPGAs has traditionally been a complex process. This training will highlight the ease with which high performance memory interfaces can be implemented and tested in Altera® 28-nm and 40-nm devices (Stratix® IV, Stratix® V, Cyclone® IV, Cyclone V, Arria® II GX, and Arria® V devices) using the Quartus® II software v. 12.1. You’ll learn how to select, parameterize, and test your memory controller IP easily by following a recommended design flow. This training focuses on creating DDR-style memory interfaces using Altera’s UniPHY self-calibrating PHY block. This PHY can be used with Altera’s memory controller IP or combined with your own custom controller. Course Objectives At course completion, you will be able to: Parameterize high-performance Altera® memory controller IP Understand the advantages of using the UniPHY auto-calibrated PHY in a design Instantiate and test high-performance memory controller IP in your design Set up and run an RTL simulation in the ModelSim®-Altera® Starter Edition software Perform a static timing analysis with the TimeQuest timing analyzer Correct some common timing problems Use on-chip debugging tools to debug interface calibration and functionality Skills Required Background in digital logic design Basic knowledge of memory interfaces Familiarity with the Quartus II software Familiarity with a simulation tool, such as the ModelSim-Altera® Starter Edition Prior exposure to the TimeQuest timing analysis tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMEM1110. FPGA_OMEM1110. <p>Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs</p>