When using the Intel® Stratix® 10 Avalon -MM Interface for PCI Express* IP Core, how can I read the PCIe* VENDOR ID register at address offset 0x000? - When using the Intel® Stratix® 10 Avalon -MM Interface for PCI Express* IP Core, how can I read the PCIe* VENDOR ID register at address offset 0x000? Description The address offset given for the PCI* Header Configuration Space Registers in the user guide is only a partial 12 Least Significant Bit (LSB) address offset(4 Kbytes PCIe configuration space). When using the optional Hard IP Reconfiguration block signals the full 21 bit hip_reconfig_address[20:0] must be driven. Resolution This clarification will be added to a future release of the user guide. To access Device Identification Registers, such as VENDOR ID etc., the MSB bit of hip_reconfig_address bus must be set to 1'b1 . #NOTE : Attempted access of undefined address space have unpredictable results and can cause the PCIe* Hard IP core to stop working, a power cycle is required to recover. Custom Fields values: ['novalue'] Troubleshooting FB: 1806677554; False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']