Why do F-Tile Ethernet FPGA Hard IP flag critical warnings for multi-instance external custom cadence variants? - Why do F-Tile Ethernet FPGA Hard IP flag critical warnings for multi-instance external custom cadence variants? Description Due to a problem with timing requirements in the Quartus® Prime Pro Edition Software version 23.3, the Quartus® Prime Pro Edition Software version 23.3 will flag a critical warning for multi-instance with external custom cadence variants. Resolution There is no workaround available. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16021955354 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']