Advanced System Design Using Platform Designer: Component & System Simulation - 28 Minutes This training is part 1 of 4. The Platform Designer system integration tool saves significant time by automatically generating interconnect logic to connect IP functions and subsystems. In this training you will learn about some advanced capabilities of the tool. In this first part, you will learn how to verify an individual component or an entire system design through simulation. You'll learn about the verification IP included in the software in the form of Bus Functional Models (BFMs), essentially golden reference components for the supported standard interfaces, and monitors. You'll see how Platform Designer makes it easy to build a testbench system and how to use a simple API in your testbench code to control the operation of the BFMs in the system during a simulation. Course Objectives At course completion, you will be able to: Know about the Verification IP Suite included with the Altera® Quartus Prime software Understand how to use Platform Designer to generate testbench systems Write testbench code using the Bus Functional Model (BFM) API to control BFMs during a simulation Skills Required Background in digital logic design Familiarity with the Altera® Quartus Prime software Familiarity with the Platform Designer system design tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (cc) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAQSYSSIM. FPGA_OAQSYSSIM. <p>Advanced System Design Using Platform Designer: Component & System Simulation</p>