Quartus 20.1 - tri state output bad generated code - Quartus 20.1 - tri state output bad generated code Hi, I'm new in FPGA world. To learn a bit more fast, I bought one kit with Cyclone IV E EP4CE6E22C8. I've found some software examples for that kit, but the programming language is Verilog. As I started with VHDL, I've found a converter software ( Icarus Verilog ) to translate the Verilog tp VHDL, which seams to work fine (with some limitations, but it does the job). One of the statements is translated to the following concurrent statements: sda <= sda_r when sda_link = '1' else tmp_ivl_0; tmp_ivl_0 <= 'Z'; The sda output should be a tri state. With the lines above, Quartus will give the following warnings : Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "sda~synth" And generate the following hardware connections: As the "sda" output must be tri state, in this conditions, the FPGA don't do the job as it should. If I change the code lines to the following: sda <= sda_r when sda_link = '1' else 'Z'; --tmp_ivl_0; The warning goes away and the connections generated are: In this situation the FPGA acts like it should. My questions are: Why those concurrent statements are not translated like it should and I need to assign the 'Z' value directly in the "else" part ? Is this a bug of Quartus or a lack of my VHDL knowledge ? Thanks for your feedback. Replies: Re: Quartus 20.1 - tri state output bad generated code Thanks for the clarification @sstrell . I know there is a lot to learn in this stuff, but I was expecting less tricky things. Replies: Re: Quartus 20.1 - tri state output bad generated code The extra signal in there does not synthesize to a tri-state I/O correctly. It depends on the device architecture, but assigning the Z directly like you do in the second example is required for Quartus to interpret it correctly, setting sda_link, in this case, as the OE.