Why does the bandwidth setting not change when using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode? - Why does the bandwidth setting not change when using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode? Description When using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode, the bandwidth setting is fixed to an optimal configuration. Hence changes to the bandwidth setting (Low, Medium, High) in this IP will not be applied to the generated MIF file. Resolution This is expected behavior. Custom Fields values: ['novalue'] Troubleshooting 1808658681 False ['fPLL Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']