Why am I seeing incorrect output clock frequencies when simulating the Altera_PLL megafunction? - Why am I seeing incorrect output clock frequencies when simulating the Altera_PLL megafunction? Description Due to a bug in the simulation models in the Quartus® II software through version 12.0, if you have multiple output clocks enabled in the Altera_PLL megafunction, the simulation results may show incorrect output frequencies. This only affects the calculation of the output clock frequency in simulation, hardware is not affected. Resolution This issue is fixed in the Quartus II software version 12.0sp1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 11.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']