Why doesn't the clock switchover feature work correctly when performing a simulation of a Stratix enhanced phase-locked loop (PLL) using two aligned clocks? - Why doesn't the clock switchover feature work correctly when performing a simulation of a Stratix enhanced phase-locked loop (PLL) using two aligned clocks? Description The clock switchover feature does not simulate correctly in this case due to a problem with the PLL models in the Quartus ® II software version 2.2. When the rising edges of the two PLL clocks occur at the same time, the PLL simultion model misses the clock edge of the second input clock during a clock switchover. This problem will not occur if your two clocks are not edge-aligned. This problem was fixed in the Quartus II software version 2.2 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']