Why is there a mismatch in the PFC width between the theory calculation and the hardware measurement in the F-tile Ethernet Hard IP design? - Why is there a mismatch in the PFC width between the theory calculation and the hardware measurement in the F-tile Ethernet Hard IP design? Description You might observe a mismatch in the PFC width between the theory calculation and hardware measurement at max PFC quanta. This is due to the alignment marker (AM) pulse window within the PCS data, which is causing this variation. Resolution Estimating the deviation of the PFC width from the expected value is impossible. Quanta variation is not quantifiable, and the variation is expected. There is no plan to fix this problem. Custom Fields values: ['novalue'] Errata 16024881303 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']