Creonic CCSDS AR4JA LDPC Encoder and Decoder - The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard. Creonic is the ISO 9001:2015 certified leader in ready-for-use IP cores, offering a rich services and product portfolio for wired, wireless, fiber, and free-space optical communications. Covering… Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block lengths 1024, 4096 and 16384 are specially designed for deep-space missions, but the excellent error correction performance makes it the ideal fit for further applications with highest demands on forward error correction. The IP cores are available for ASIC and FPGAs. Aerospace Wireless Creonic CCSDS AR4JA LDPC Encoder and Decoder Key Features Support for code rates 1/2, 2/3, and 4/5 Offering Brief No No No No C/C++ Verilog VHDL Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA No Yes 22.4.0 Offering Brief Production a1JUi0000049U94MAE What's Included Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model Ordering Information Creonic CCSDS AR4JA LDPC Encoder and Decoder a1JUi0000049U94MAE Production Intellectual Property (IP) Communication a1MUi00000BO8rZMAT a1MUi00000BO8rZMAT Select 2026-04-21T12:58:30.000+0000 The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard. Partner Solutions