VHDL error "Error: Unknown formal identifier pll_slf_rst" and Verilog error "Error: Unresolved defparam reference to pll_slf_rst" generated when simulating ACDS 13.1 update 3 designs - VHDL error "Error: Unknown formal identifier pll_slf_rst" and Verilog error "Error: Unresolved defparam reference to pll_slf_rst" generated when simulating ACDS 13.1 update 3 designs
Description After installing the Altera® Complete Design Suite version 13.1 update 3, you might see an error message when simulating designs targeting Arria® V, Cyclone® V, or Stratix® V devices with Altera PLL IP with the Mentor Graphics® ModelSim®-Altera software. The error message for VHDL users is: Error: Unknown formal identifier “pll_slf_rst” The error message for Verilog users is: Error: Unresolved defparam reference to “pll_slf_rst” Resolution This issue has been fixed in the Quartus® II software release version 14.0. To eliminate the error in the Quartus II software release version 13.1 update 3, compile the following files into a local library directory, and map the libraries altera_lnsim and a ltera_lnsim_ver to the local library directory: quartus\eda\sim_lib\altera_lnsim.sv quartus\eda\sim_lib\altera_lnsim_components.vhd (VHDL only)
Custom Fields values:
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Troubleshooting
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True
['PLL']
['FPGA Dev Tools Quartus II Software']
14.0
13.1.3
['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs']
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['novalue']
['novalue'] - 2021-08-25
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