Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to place 50G-2 OTN Variant in FHT0 and FHT1 location ? - Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to place 50G-2 OTN Variant in FHT0 and FHT1 location ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the F-Tile Ethernet Intel® FPGA Hard IP Design Example will fail to place the 50GE-2 Variant (all modes) in FHT0 and FHT 1 location. Resolution The 50GE-2 Variant can be placed in FHT2 and FHT3 locations. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 16013451913 True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']