False Timing Failures in QDR-IV Interfaces on Arria 10 Devices - False Timing Failures in QDR-IV Interfaces on Arria 10 Devices Description This problem affects QDR-IV interfaces on Arria 10 devices. The following I/O timing failures are likely to be reported: DK versus CK timing is likely to fail, because the current timing model assumes that DK/CK calibration is not performed, but in reality DK/CK calibration is performed. Write timing is likely to fail, because the current timing model is incorrect. The two timing failures described above are false, and can be ignored. Resolution There is no workaround for this issue. This issue is fixed in version 15.0. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.0 14.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']