Why does compiling the PHY Lite for Parallel Interfaces IP example design for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate invalid Fitter assignment warnings? - Why does compiling the PHY Lite for Parallel Interfaces IP example design for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate invalid Fitter assignment warnings? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that the PHY Lite for Parallel Interfaces IP example design compilations for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate a warning message on invalid Fitter assignments. The following assignments are invalid and listed in the Ignored Assignments panel in the Fitter Compilation Report: Can Relax Periphery to Core Hyper Register Constraint TOP_FEEDBACK_DELAY_STEP TOP_FEEDBACK_DELAY_SEL BOT_FEEDBACK_DELAY_STEP BOT_FEEDBACK_DELAY_SEL Resolution There is no workaround for this problem in the Quartus® Prime Pro Edition Software version 25.3. The invalid assignments can safely be ignored. The compilation and simulation results are valid. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 22021601686 False ['PHY Lite for Parallel Interfaces IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']