Cannot enable SPIM0 and SPIS0 routing to FPGA at the same time. Disable one of these in Advance FPGA Placement - Cannot enable SPIM0 and SPIS0 routing to FPGA at the same time. Disable one of these in Advance FPGA Placement Description The Quartus Prime software does not allow the routing of both the SPI master (SPIM) and SPI slave (SPIS) interfaces to the FPGA fabric simultaneously for the same SPI instance. This restriction applies to SPIM0/SPIS0 and SPIM1/SPIS1. Resolution When configuring SPI routing to the FPGA, enable either the master or the slave interface for each SPI instance, but not both at the same time. For example: SPIM0 and SPIS0 cannot be enabled together SPIM1 and SPIS1 cannot be enabled together Custom Fields values: ['novalue'] Troubleshooting 14025922696 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']