Why do multiple pulses occur on flr_received signals when host do function level reset to an endpoint device of Scalable Switch IP for PCI Express*? - Why do multiple pulses occur on flr_received signals when host do function level reset to an endpoint device of Scalable Switch IP for PCI Express*? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and later, you may see multiple pulses on flr_received signal of Scalable Switch IP in FLR operation. Resolution To work around this problem, you should respond to flr_completed signal for each pulse on flr_received. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting QS-343513 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']