Timing constraints on PLL - Timing constraints on PLL Do we have to constrain the clocks that are generated through the PLL? I am currently using Intel MAX 10 FPGA. Replies: Re: Timing constraints on PLL I’m believed I have addressed your question. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Best Regards, Richard Tan p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. Replies: Re: Timing constraints on PLL Yes, you may checkout the User Guide below. https://www.intel.com/content/www/us/en/docs/programmable/683081/17-1-1/pll-clocks.html Best Regards, Richard Tan p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. - 2022-01-12