Why do the design examples for the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps variants send an incorrect number of packets? - Why do the design examples for the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps variants send an incorrect number of packets? Description When using the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, when creating a design example with the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps base variants, operating in fixed and incremental modes send an incorrect number of packets. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, stop the running project and restart the device. This problem has been fixed starting in the Intel® Quartus® Prime Pro edition software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1409630957 False ['25G Ethernet IP', 'Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Stratix® 10 DX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']