Do the PLL_[T1,T2,B1,B2]_CLKOUT0p/n pins on column I/O for Stratix IV devices support true LVDS? - Do the PLL_[T1,T2,B1,B2]_CLKOUT0p/n pins on column I/O for Stratix IV devices support true LVDS? Description Yes, PLL_[T1,T2,B1,B2]_CLKOUT0p/n pins in Stratix ® IV devices support true LVDS in column I/O banks. General purpose I/O pins located on column I/O banks support emulated LVDS as stated in I/O Features in Stratix IV Devices (PDF). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']