Why are the xgmii_rx_dc[71:0] and xgmii_rx_clk signals not synchronized to rx_coreclkin during simulation of the 10GBASE-R PHY IP in Stratix® V GX devices when using the Quartus® II software v12.0? - Why are the xgmii_rx_dc[71:0] and xgmii_rx_clk signals not synchronized to rx_coreclkin during simulation of the 10GBASE-R PHY IP in Stratix® V GX devices when using the Quartus® II software v12.0? Description Due to a bug in the 10GBASE-R PHY simulation model of the Quartus® II software version 12.0, the xgmii_rx_dc[71:0] and xgmii_rx_clk signals are not synchronized to rx_coreclkin . Resolution To work around this problem, use the non-encrypted 10GBASE-R PHY simulation models in the following method: Open the altera_xcvr_10gbaser.sv System Verilog file in the <instance_name>_sim\altera_xcvr_10gbaser folder with a text editor. Add the line commented in the following example: sv_xcvr_10gbaser_nr #( .num_channels (num_channels ), .operation_mode (operation_mode ), .sys_clk_in_mhz (mgmt_clk_in_mhz ), .ref_clk_freq (ref_clk_freq ), .rx_use_coreclk (rx_use_coreclk ), //add this line .pll_type (pll_type ), .RX_LATADJ (rx_latadj), .TX_LATADJ (tx_latadj)) Open the msim_setup.tcl file in the <Instance_name>_sim\\mentor folder. Comment out all lines with "mentor" in the path. To use the updated System Verilog simulation model in mixed language simulation, you need mixed-language ModelSim license. This problem is fixed in the Quartus II software v12.0. Custom Fields values: ['novalue'] Troubleshooting FB : 53024 False ['Generic Component'] ['FPGA Dev Tools Quartus II Software'] 12.0 12.0 ['Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']