Due to a problem in the Quartus® II software version 12.1 and later, you may see this error in Stratix® V devices when using the ALTLVDS_TX megafunction in external PLL mode. - Due to a problem in the Quartus® II software version 12.1 and later, you may see this error in Stratix® V devices when using the ALTLVDS_TX megafunction in external PLL mode. Description Due to a problem in the Quartus® II Software version 12.1 and later, you may see this error in Stratix® V devices when using the ALTLVDS_TX mega function in external PLL mode. Error: SERDES transmitter node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|outclock_tx' is not properly connected on the 'ENABLE0' port. It must be connected to one of the valid ports listed below.Info: Can be connected to LOADEN port of stratixv_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of generic_pll WYSIWYG Resolution To workaround this problem, an LVDS buffer needs to be inserted between the external pll and the ALTLVDS instance on the tx_inclock and the tx_enable ports. Please review the article below to learn how to add an intermediate LVDS buffer between the external PLL and ALTLVDS IP. This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 12.1. Related Articles How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone V, Arria V, and Stratix V devices? Custom Fields values: ['novalue'] Troubleshooting 2205792132 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.1 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']