When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled, why does the fitter fail if using the EHIP 1/3 IEEE1588/PTP channel placement restriction? - When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled, why does the fitter fail if using the EHIP 1/3 IEEE1588/PTP channel placement restriction? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.1 software, the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled cannot pass fitter compilation if using EHIP 1/3 as the channel placement restriction. Resolution To work around this error, use EHIP 0/2 instead of EHIP 1/3 as the channel placement restriction. This problem has been fixed starting in v19.2 of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 1507229498 True ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.2 19.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']