IntelliProp ECC with BCH Algorithm (Single code; Single Correction) IP Core (IPC-BL119A-ZM) - The "Commander" of low-latency reliability; a highly configurable BCH ECC IP core providing single-bit correction with a minimal logic footprint for high-performance Altera-based systems. IntelliProp is a leading innovator of high-performance Intellectual Property (IP) cores and Application-Specific Standard Products (ASSPs), specializing in the Memory and Data Storage industry… Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Agilex™ 7 FPGA F-Series Stratix® 10 AX FPGA In high-speed storage and communication environments, timing is everything. While modern NAND often demands heavy multi-bit correction, the IPC-BL119A-ZM stands as the industry's "Commander" of resource-efficient reliability. It is specifically engineered for systems where a tiny logic footprint and deterministic, single-digit nanosecond timing are non-negotiable. By providing a hardware-level "Gold Standard" for single-bit correction (SEC) and double-bit error detection (DED), this core allows Altera engineers to guarantee data integrity without sacrificing the performance or fabric space of their primary application. It operates in-line with the data path to detect and repair errors in real-time, making it an essential component for industrial, medical, and aerospace applications using SLC NAND flash or SRAM. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation IntelliProp ECC with BCH Algorithm (Single code; Single Correction) IP Core (IPC-BL119A-ZM) Key Features Algorithm: Robust BCH implementation for 1-bit correction/2-bit detection. Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Agilex™ 7 FPGA F-Series Stratix® 10 AX FPGA Yes Agilex™ 7 FPGA Starter Kit Yes 25.3.0 Offering Brief Production a1JUi0000049UFQMA2 What's Included Encrypted Verilog RTL Ordering Information IPC-BL119A-ZM a1JUi0000049UFQMA2 Production Intellectual Property (IP) a1MUi00000BO8sHMAT a1MUi00000BO8sHMAT Select 2026-04-28T20:33:53.000+0000 The "Commander" of low-latency reliability; a highly configurable BCH ECC IP core providing single-bit correction with a minimal logic footprint for high-performance Altera-based systems. Partner Solutions