Error (16812): Verilog HDL error at altera_up_sync_fifo.v(138): port connections cannot be mixed ordered and named. Or there might be a trailing comma in named port connection. - Error (16812): Verilog HDL error at altera_up_sync_fifo.v(138): port connections cannot be mixed ordered and named. Or there might be a trailing comma in named port connection. Description Due to a problem in the Intel® Quartus® Prime Pro and Standard Edition software version 17.1 Update 1 and earlier, you might see this syntax error when compiling the RS232_UART IP generated using Platform Designer. Resolution To work around this problem edit the IP HDL file “\altera_up_avalon_rs232_\synth\altera_up_sync_fifo.v” to update the syntax Error in scfifo instance. Remove the "," at the end of line 129 and add it back after //synopsys translate_off on line 133 Original Code: scfifo Sync_FIFO ( // Inputs .clock (clk), .sclr (reset), .data (write_data), .wrreq (write_en), .rdreq (read_en), // Bidirectionals // Outputs .empty (fifo_is_empty), .full (fifo_is_full), .usedw (words_used), .q (read_data), // Unused // synopsys translate_off .aclr (), .almost_empty (), .almost_full () // synopsys translate_on ); Modified Code: scfifo Sync_FIFO ( // Inputs .clock (clk), .sclr (reset), .data (write_data), .wrreq (write_en), .rdreq (read_en), // Bidirectionals // Outputs .empty (fifo_is_empty), .full (fifo_is_full), .usedw (words_used), .q (read_data) // Unused // synopsys translate_off , .aclr (), .almost_empty (), .almost_full () // synopsys translate_on ); This problem is fixed beginning with the Intel Quartus Prime Pro and Standard Edition software version 18.0 Custom Fields values: ['novalue'] Troubleshooting FB: 529105; False ['RS232 UART IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']