Sub -LVDS IO standard - Sub -LVDS IO standard Hello , I have one image sensor with 20 lane Sub-LVDS output (16 lane data and 4 lane clock) with following dc characteristics Symbol Description Min. Typical Max Condition VDD_IO IO digital Supply 1.71 V 1.8 V 1.89 V ROD Differential output termination 79.4 Ω 100 Ω 123.5 Ω when in differential mode VOD Output differential p-p voltage 0.262 V 0.54 V when in differential mode VOCM Output common mode voltage 0.9 V when in differential mode i am looking for a FPGA based bridge which will convert the Sub-LVDS output to MIPI CSI-2 format. could you please suggest a FPGA (with 50-60K LUT/Logic elements) which serve this application? i have gone through few FPGA device but couldn't find any appropriate device which will receive the specified IO standard. Replies: Re: Sub -LVDS IO standard As we do not receive any response from you on the previous reply have been provided, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. p/s: If any of the answers from the community or Intel Support are helpful, please feel free to give "Kudos" or rate a 4/5 for the evaluation survey. Replies: Re: Sub -LVDS IO standard Hello, No worries! With that, may I know, do you need more support for this? Regards, Aqid Replies: Re: Sub -LVDS IO standard Hello guys, I really appreciate the your efforts. From your suggestions, i could make the conclusion that to interface the sub LVDS i need to check the IO receiver standard specifically i need check the VICM range along with receiver swing range. Also we need to careful about choosing the DDR LVDS receiver speed as well. Replies: Re: Sub -LVDS IO standard From what I understand, LVDS receiver are capable of being driven by sub-LVDS driver although the Vcm and Vid levels are reduced from typical LVDS. However, if you refer to Intel Max 10 datasheet, there are supported sub-LVDS I/O standard listed in the table for your reference. You can refer below link: https://www.intel.com/content/www/us/en/docs/programmable/683794/current/differential-i-o-standards-specifications.html However Replies: Re: Sub -LVDS IO standard hello there , Thank you very much for your response! accept my apologies to not providing clock details , here are the clock details, "Synchronous serial output with sub-LVDS levels 16 data lanes with 4 clock lanes (total of 20 lanes, 10 for even rows and 10 for odd rows) data transfer rate: 1100 Mbps for maximum frame rate DDR clock for synchronization at 550 MHz" Could you please enlighten me little about selecting sub LVDS receiver dont we need to check about differential voltage swing ? as i mentioned my data have output swing can be 0.262V to 0.54V i went through different data available on google about subLVDS i can see there receiver input threshold are there could you please explain how they work ? Replies: Re: Sub -LVDS IO standard hello there , Thank you very much for your response! accept my apologies to not providing clock details , here are the clock details, "Synchronous serial output with sub-LVDS levels 16 data lanes with 4 clock lanes (total of 20 lanes, 10 for even rows and 10 for odd rows) data transfer rate: 1100 Mbps for maximum frame rate DDR clock for synchronization at 550 MHz" Could you please enlighten me little about selecting sub LVDS receiver dont we need to check about differential voltage swing ? as i mentioned my data have output swing can be 0.262V to 0.54V i went through different data available on google about subLVDS i can see there receiver input threshold are there could you please explain how they work ? Replies: Re: Sub -LVDS IO standard This is the link: https://www.intel.com/content/www/us/en/docs/programmable/683828/current/differential-i-o-standards-specifications.html Replies: Re: Sub -LVDS IO standard Hereby I give you the Cyclone 10 GX Differential I/O pin datasheet for you to look into. It may fit your requirement. Replies: Re: Sub -LVDS IO standard Hi, if you read FPGA datasheets, you'll see that LVDS receivers of most FPGA series support Sub-LVDS level (Vicm=0.9V) with limited data rate, e.g. Cyclone 10 up to 700 MBPS. You didn't mention speed requirements but I guess that's sufficent for your application. You also need Gigabit Transceivers to send out MIPI CSI-2. Cyclone 10 GX would be my first choice.