Understanding Device Architecture - This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working… FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA. It covers programmable logic history, the complete Altera device portfolio, internal FPGA fabric architecture (ALMs, memory, DSP, clocking, I/O), the Quartus Prime design flow from RTL entry through synthesis, timing closure, pin planning, and device programming, plus the high speed connectivity features (transceivers, hard IP, DDR interfaces) common to mid range and high end families. The curriculum closes with simulation, on-chip debug, partial reconfiguration, and device selection methodology. The first optional follow-on session covers SoC FPGA architecture, Hard Processor System internals, AXI bridge and peripheral integration, Linux bring-up, Agilex SoC platforms, and hardware/software co-debug. Relevant to engineers working with Cyclone V SoC, Arria 10 SoC, Stratix 10 SoC, or any Agilex SoC FPGA. The second optional follow-on session discusses Agilex generation architectural innovations (Hyperflex, EMIB, Foveros), power architecture and estimation, device security and Secure Device Manager (SDM), board level signal integrity, PDN design, and thermal management. Relevant to engineers targeting high performance or production grade Agilex designs. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Understanding Device Architecture Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA 3 Days No No English Offering Brief Production Windows,Linux a1JUi000009ZJFVMA4 Basic understanding of digital logic. Familiarity with at least one HDL. General knowledge of computer hardware concepts (buses, memory, processors). Ability to use a Windows 11 or Linux desktop environment and install software. Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers What's Included PDF of slides, lab manual and lab files where applicable Ordering Information Understanding Device Architecture a1JUi000009ZJFVMA4 Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-07-16T20:43:22.000+0000 This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA. Partner Solutions