Why do I see the PCIe core clock frequency at 12.5MHz under the Clock Settings tab of Qsys GUI? - Why do I see the PCIe core clock frequency at 12.5MHz under the Clock Settings tab of Qsys GUI? Description If you set the number of lanes to 2 for the IP Compiler for PCI Express, the PCIe core clock frequency would be displayed as 12.5MHz at the Clock Settings tab of Qsys GUI. Resolution To get around this issue, you can modify line#1503 of pcie_parameters_validation.tcl in (<Quartus II installation directory>\ip\altera\altera_pcie\altera_pcie_avmm) From: set_parameter_value core_clk_freq 125 To: set_parameter_value core_clk_freq 1250 Custom Fields values: ['novalue'] Troubleshooting 2205889347 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1.1 11.0.1 ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']