Why are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs? - Why are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs? Description Due to a problem in the Quartus® Prime Pro Edition Software versions 23.2 to 25.1, you might have functional failures after partial reconfiguration (PR) in some Agilex™ FPGA devices. The failure has FPGA unit and design dependencies and does not occur in all devices. It is a time zero failure for the affected FPGA units. The problem affects all Agilex™ FPGA portfolio devices. Resolution To work around this problem: Convert your base SOF to RBF/JIC/RPD* (Base bitstream for full-chip configuration) and PR PMSF to RBF (PR bitstream) using the Quartus® Programming File Generator v25.1.1. Use the Quartus® Programmer v25.1.1 to program the Base and PR bitstreams. The problem is fixed starting with the Quartus® Prime Pro Edition Software version 25.1.1. *RPD file format is for third party programming methods, not supported in Quartus® Prime Programmer. Custom Fields values: Troubleshooting 15017649630 ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 23.4 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 3 FPGAs and SoCs']