Implementing the Hybrid Memory Cube Controller IP in an Altera FPGA - 32 Minutes Hybrid Memory Cube, or HMC, is the next generation of high-speed external memory technology. Multiple DRAM layers are connected to a logic base layer to form a 3-D, high capacity, small footprint package. Instead of the parallel interface used in traditional DDR-type memory, HMC uses high-speed transceiver links, abstracting away the complexities of DRAM timing. In this training, you'll learn how to add the HMC Controller IP to your Arria® 10 design. You'll know how to generate an example design that can help you get started quickly. You'll learn about the additional blocks that need to be added to complete the design, including an I2C master and one or more transmit PLLs. In the process, you'll learn about transceiver clocking options in Arria® 10 devices. Course Objectives At course completion, you will be able to: Know how to Implement an Altera® FPGA design that can access a Hybrid memory Cube device Skills Required Background in digital logic design Familiarity with the Quartus Prime software Familiarity with high-speed transceivers If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHMC102. FPGA_OHMC102. <p>Implementing the Hybrid Memory Cube Controller IP in an Altera FPGA</p>