MAC-SeC-MG - The MAC-SEC-MG from CAST is a high-performance hardware MACsec IP core designed to provide robust security for 2-16.75 Gbps Ethernet networks. It fully implements the IEEE 802.1AE-2018 and IEEE 802… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® II FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA The MAC-SEC-MG IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports the AES-GCM and AES-GCM-XPN cipher suites provisioned by the MACsec standard and the VLAN-in-Clear im-provement. The engine is silicon- and performance-optimized for networks operating from 2.5 Gbps to 10 Gbps and beyond; up to 16.75 Gbps is possible with this core. Featuring a configurable number of Security Associations (up to 64k), this protocol engine supports multiple security channels and can implement multiple Security Entities (SecYs). It operates in full-duplex mode at line speed in each direction for 2.5 Gbps to 16.75 Gbps connections. It does so by implementing a 128-bit wide data path, which provides adequate performance while minimizing silicon re-sources. Designed for ease of integration, the MAC-SEC-MG core is a fully synchronous, single-clock domain design that uses standardized inter-faces and can be optionally pre-integrated with companion cores available from CAST. The control and status registers of the core are accessible via a generic 32-bit memory-mapped slave interface. Interface bridges deliv-ered with the core can convert this generic host interface to a 32-bit AMBA® APB or AHB-Lite, Avalon®-MM, or Wishbone interface. Pack-et data are input and output via AXI Stream interfaces with configurable data width, enabling direct connection to Ethernet MACs, PTP timestamping units, or other higher-layer protocol engines. Interface bridges and a DMA engine capable of driving the AXI Stream inter-faces are available separately. They can be used in cases where moving data to and from the core is preferable over a memory-mapped bus. The core can be delivered pre-integrated with the Low-Latency Ethernet MAC or any Ethernet TSN cores available from CAST. Ethernet Access Aerospace Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Transportation Wireless MAC-SeC-MG Key Features Compliant with IEEE 802.1AE-2018 and IEEE 802.1AEbw Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® II FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi000008BsBlMAK What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information MAC-SEC-MG a1JUi000008BsBlMAK Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:33.000+0000 The MAC-SEC-MG from CAST is a high-performance hardware MACsec IP core designed to provide robust security for 2-16.75 Gbps Ethernet networks. It fully implements the IEEE 802.1AE-2018 and IEEE 802.1AEbw standards, supporting GCM-AES and GCM-AES-XPN encryption modes with 128- and 256-bit keys. The core features a 128-bit wide data path and operates at line speed in full-duplex mode, ensuring low-latency and secure communication. It supports up to 64k security associations and multiple security channels and entities, making it suitable for both simple LAN deployments and complex WAN architectures. MAC-SEC-MG integrates easily with Ethernet MACs, including CAST’s Low-Latency eMAC, and can work alongside networking protocol stacks such as UDP/IP and TCP/IP. Its standardized interfaces and high configurability make it ideal for automotive, industrial, and IoT edge applications, providing reliable encryption, authentication, and integrity protection for sensitive Ethernet traffic. Partner Solutions