Conflicting Pin Assignment Error with UART0 - Conflicting Pin Assignment Error with UART0 Description If your HPS design was created with Qsys v13.0 or earlier, and you open it in v13.0 SP1 or later, you might see an error message similar to the following: The selected peripheral UART0 and <component name> are conflicting. In v13.0 and earlier, the HPS soft IP component for the Arria V SoC HPS has incorrect pin set definitions. The UART0 pin assignments in HPS I/O Set 0 and HPS I/O Set 2 are interchanged. When you open a design created with the incorrect pin set definitions, the swapped pin locations overlap with other component pins. Resolution To work around this issue, perform the following steps: Open your SoC HPS design in Qsys. Edit the HPS component. Open the Peripheral Pin Multiplexing page. Change UART0 pin multiplexing from HPS I/O Set 0 to HPS I/O Set 2 , or vice-versa. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 12.1 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']