What is the latency of the transceiver rx_syncstatus signal de-asserting after the assertion of the rx_enapatternalign signal in Stratix IV GX/T, Arria II GX/Z and Cyclone IV GX devices? - What is the latency of the transceiver rx_syncstatus signal de-asserting after the assertion of the rx_enapatternalign signal in Stratix IV GX/T, Arria II GX/Z and Cyclone IV GX devices? Description The latency of the transceiver rx_syncstatus signal de-asserting after the assertion of the rx_enapatternalign signal in Stratix® IV GX/T, Arria® II GX/Z and Cyclone® IV GX devices is dependent upon the implemented Rx PCS datapath. The Word Aligner block is the first block in the PCS datapath. The rx_enapatternalign signal is an asynchronous input to the Word Aligner block. The rx_syncstatus signal is a synchronous output from the Word Aligner block and has the same latency as the Rx PCS datapath. Therefore the latency of the rx_syncstatus de-asserting after the assertion of the rx_enapatternalign signal is equal to the PCS datapath latency from the Word Aligner. Diagrams implying the latency to be one rx_clkout clock cycle in the Stratix IV GX/T, Arria II GX/Z and Cyclone IV GX device handbooks will be updated in due course. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']