RapidIO II IP Core Does Not Capture Control Bits Correctly in IMPL_DEPENDENT Field of Port 0 Attributes Capture CSR - RapidIO II IP Core Does Not Capture Control Bits Correctly in IMPL_DEPENDENT Field of Port 0 Attributes Capture CSR Description When the RapidIO II IP core receives a data packet with an error, the IP core should capture the control bits of the first 16 packet characters in the IMPL_DEPENDENT field of the Port 0 Attributes Capture CSR at offset 0x348. However, in this case the IP core sets the value of the register field to 16’b0 instead. Resolution This issue has no workaround. This issue will be fixed in a future version of the RapidIO II IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0a10 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']