HLS Loop Optimizations (Part 3 of 7) - 82 Minutes In the class, you will learn how to use the Altera® HLS Compiler to optimize loops in your HLS component. We will cover the basic concepts of loop pipelining and loop unrolling and present common techniques to optimize your loops. Course Objectives At course completion, you will be able to: Understand loop execution Model use common techniques to improve the pipeline performance of loops Effectively use pragmas to improve the performance of loops resource share using loops Skills Required Basic understanding of the C++ programming language Basic understanding of FPGAs and the Altera® Quartus Development Environment If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHLS3. FPGA_OHLS3. <p>HLS Loop Optimizations (Part 3 of 7)</p>