Hard Memory Interface May Fail VHDL Simulation in Arria V and Cyclone V Devices - Hard Memory Interface May Fail VHDL Simulation in Arria V and Cyclone V Devices Description This problem affects DDR2 and DDR3, LPDDR2, QDR II, RLDRAM II, and RLDRAM 3 products. Hard memory interfaces on Arria V and Cyclone V devices may fail VHDL simulation with NC Sim or Aldec Riviera-PRO. Resolution The workaround for this issue is to open the generated altera_mem_if_hard_memory_controller_top_arriav.sv file and remove the following parameters: VECT_ATTR_COUNTER_ONE_MASK VECT_ATTR_COUNTER_ONE_MATCH VECT_ATTR_COUNTER_ZERO_MASK VECT_ATTR_COUNTER_ZERO_MATCH VECT_ATTR_DEBUG_SELECT_BYTE This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']