Altera® Stratix® 10 FPGA L- and H-Tile Transceiver Basics - Same Course in Simplified Chinese: Altera® Stratix® 10 收发器基础 Same Course in Japanese: インテル® Stratix® 10 FPGA トランシーバー基礎編 56 Minutes Altera® FPGAs contain embedded transceivers that support the wide range of I/O bandwidth requirements of systems using high-performance FPGAs. This online course provides an overview of the transceivers found on the Altera® Stratix® 10 family members with L- and H-tiles. This training is the first step in learning how to build a high-performance interface, particularly if your interface needs are more customized, or non-standard. By the end of this training, you will be able to define the blocks found in the transmitter and receiver data paths as well as how the blocks are used to ensure successful data transfers across high-speed serial links. Course Objectives At course completion, you will be able to: Describe the blocks found in the transmitter and receiver paths of Altera® Stratix® 10 FPGA L and H-tile high-speed serial transceivers Describe how each transceiver block is used in supporting a high-speed serial interface Skills Required Background in digital logic General understanding of FPGA architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS101115. FPGA_OS101115. <p>Altera Stratix 10 FPGA L- and H-Tile Transceiver Basics</p>