SOPC Builder-generated Systems Cannot Serve as Top-Level Design for UniPHY External Memory Interfaces - SOPC Builder-generated Systems Cannot Serve as Top-Level Design for UniPHY External Memory Interfaces Description Systems generated with SOPC Builder cannot serve as the top-level design, because SOPC Builder automatically exports the parallelterminationcontrol and seriesterminationcontrol OCT control signals as top-level ports, but these signals must not be exposed at the top level. Resolution Perform either of the following procedures to work around this issue: Create a top-level wrapper which instantiates the SOPC Builder-generated system, and does not make any connection to the parallelterminationcontrol or seriesterminationcontrol signals. or Open the top-level SOPC Builder system file (for example, system.v), and delete the wire names from within the brackets for the parallelterminationcontrol and seriesterminationcontrol signals for all UniPHY cores. The resulting lines should appear as follows: .parallelterminationcontrol () .seriesterminationcontrol () The wire names that you delete from within the brackets must also be removed from all other locations in the top-level system file, including the top-level port list. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']