<your_ip>.regmap file not generated when using the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core is generated? - <your_ip>.regmap file not generated when using the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core is generated?
Description UG-20160 | 2020.06.29 and earlier versions indicate that the file <your_ip>.regmap will be created when generating the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core. This is incorrect. The file <your_ip>.regmap is not generated. Resolution This mistake has been removed from the IP Core Generated Files table, updated for version 20.2 of the Intel® Quartus® Prime Design Suite.
Custom Fields values:
['novalue']
Troubleshooting
1508021320
False
['Ethernet']
['FPGA Dev Tools Quartus® Prime Software Pro']
20.2
19.4
['Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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